RTLery Library, now contains clock domain crossing synchronizers. The most common asynchronous FIFO synchronizer, based on an embedded memory and Grey code encoding, can be used for passing data between any asynchronous clock domains. The slow signal synchronizer is best used for clock domain crossing of configuration and control busses, offering safe vector synchronization using low flop count.

The asynchronous FIFO synchronizer offers a solution for transferring signals and vectors across clock domains without risking meta-stability and coherency problems resulting from partial vector synchronization. The synchronizer allows the transfer of wide vectors across clock domain with minimal timing requirements and no meta-stability issues. The synchronizer uses a FIFO with one clock domain for load and another clock domain for extract. Data is written into the FIFO at one clock domain, and only later is read from the FIFO in the other clock domain. The FIFO itself can be implemented using an embedded memory or an array of registers.

Slow signal synchronizer offers a solution for transferring relatively slow and static vectors across clock domains without risking meta-stability and coherency problems resulting from partial vector synchronization. The synchronizer is most suitable for configuration and status synchronization. The synchronizer allows the transfer of wide vectors across clock domain independently of clock frequency ratio and with minimal timing requirements.

check out the synchronizers section