glitch free clock multiplexer(mux)





     
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A clock glitch-free clock multiplexer serves to switch between two asynchronous clocks while protecting downstream logic from clock glitches. The de-glitch clock mux also enables switching when one or both of the clocks are not toggling. This component contains the verified RTL code of the clock switch as well as documentation and timing and physical design instruction. Clock multiplexing is required for clean transition from one clock source to another. The main issue with clock multiplexing is to prevent glitches or unexpected clock pulse that may be too short for parts of the logic.  

For clocks of different frequencies, or in cases where one of the clocks may not be toggling, the situation is even more complicated, as the switching is required to ensure no clock edges will be occurring during the clock switch.

This solution enables safe glitch free clock multiplexing and clock toggling detection, so even if one of the clocks is not toggling, the multiplexing is performed correctly. During the transition, the clock is stopped for a short period, and then restarts from the other clock source.

Block Diagram

clock deglitch mux block diagram

 

Features

  • Glitch free clock multiplexing
  • Separate control clock for switching logic, can be any free running clock.
  • Based on clock gating with a “quiet” period between the two clocks.
  • Clock toggling detection, enabling the mux to change even if one clock is not toggling.
  • Select signal change triggers the switch sequence.
  • Control signal for stopping the output clock using the clock gates.
  • Indication of “switching in progress” for integration into control logic.

Product deliverables

  • Verified RTL code and simulation test-bench
  • Access to detailed design documentation
  • One year support and customization service.


glitch free clock multiplexer(mux) documentation

 

Parameters table

Parameter

Valid values

description

MAXRATIOCNTRSIZE

Log(2) of MAXRATIO rounded up

Width of the binary representation of the maximal relation between the controlclk and any of the clocks clk0 and clk1. This parameter will be used for the timeout counter of the toggle detection logic. The MAXRATIOCNTRSIZE parameter setting is necessary when the controlclk is faster than clk0 and clk1. In the case where it is slower or equal, this parameter should be set to a value of 4.

Interface table

Signal name

Direction/width

description

Clk0

Input

Clock 0 to be selected

Clk1

Input

Clock 1 to be selected

Controlclk

Input

Control clock, used for controlling the switch logic and detection logic.

resetb

Input

Asynchronous active low reset, used for resetting the control logic.

Select

Input

Select signal, selects clk0 when 0 and clk1 when 1

Test mode

Input

When enabled, clk0 is selected.

Stopclocks

Input

Stop both clocks, while asserted, the select signal will not have any affect.

Switch_in_progress

Output

Asserted during the switch sequence. When at 0, the Clkout is stable.

Clkout

Output

Muxed clock output

Switching logic

The clock switching logic generates a sequence of operations where both clocks are stopped, and then the newly selected clock is started after the mux has changed.

The switch logic will only switch the mux after both clocks are verified to be off or in the case one of them is inactive, as indicated by the toggle detection logic.

During the switching progress, the Switch_in_progress signal would be asserted. This will enable external control logic to initiate a switch and wait until it is verified to have happened.

The below waveform shows the process of mux changing, the actual clock change is in the middle of the clock stop window.

Clock_select is the signal controlling the actual clock mux

Enable_ck1,0 are controlling the clock gating of the respective clocks.

 

clock deglitch mux switching waveform

 

Toggle detection

To prevent glitches, the switching logic requires knowing if one of the clocks has stopped toggling. The toggle detection, is a timeout on the clock edges, so if for a period of time, there was no edge detected, the timeout would expire and the mux logic would consider the clock stopped.

The MAXRATIOCNTRSIZE parameter setting is required if the controlclk is faster than clk0 and clk1. In the case where it is slower, this parameter should be set to a value of 4.

Note: the detection logic is limited to long term changes of the clock status. Is the clock stops for short periods, it may not function correctly. Using a parameter which is too small for the MAXRATIOCNTRSIZE may also result is wrong detections of clock stops.

Stop clocks

The stopclocks signal enables the use of the built-in clock gates to stop the clocks to the downstream logic when necessary. While the clocks are stopped, the select change will have no effect. The switch in progress will be asserted during the period between the assertion of the stopclocks signal and the time where both clocks are verified to be stopped. The same would happen when stopclocks is de-asserted. An external logic can monitor the signal to ensure clocks have changed.

Reset

The reset of the clock mux is asynchronous and is used for all 3 clock domains of the component.

 

Replacing the clock gating cells

The core is supplied with a temporary standard cells library that should be used only for simulation. The clock gating cell and mux cell that resides inside the clkmux module should be replaced by cells from the standard cells library used for the device.

The clock gating cell contains a negative edge latch and its logical definition in most libraries is similar to the below drawing.

 

Application notes and warnings

The detection logic is limited to long term changes of the clock status. If the clock stops for short periods, it may not function correctly.

 

Using a parameter which is too small for the MAXRATIOCNTRSIZE may also result is wrong detections of clock stops. If the contrlclock is faster than the slowest clock, the propper ratio parameter should be defined, allowing the toggle detection logic to correctly identify when the slower clock has stopped.

 

It is preferable that starting or stopping the clock would not be happening at the same time as mux switching from one clock source to the other. For the case that this is done in very close proximity, glitches may occur as there is no way to determine if the clock started right in the middle of a mux switch sequence. To prevent such issues the clocks should not be started or stopped during a switch operation and for a period of 16 clock cycles before and after the switch.

 

For all cases where each of the clocks is stable either running or stopped, the switching would be performed without glitches.

Test Items

the below table summarizes the test items that were checked

Item name

Description

Clock switching

Check clock switching with both clocks active, at different clock frequency relation.

One clock off

Check clock switching from and to a clock which is not toggling, check minimal timeout of 16 controlclocks

Two clocks off

Check switching when two clocks are off

Check fast change of select

Check that changes are ignored during the switch sequence.

clock stop Check clock stop feature, see clock is stopped and resumed at the output.

marginal toggling timeout

Check that there are not false switching and the sequence completes.

 

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application/zip icon clock_deglitch_mux.rev_2.zip (1 download)
  • Glitch free clock multiplexing
  • Separate control clock for switching logic, can be any free running clock.
  • Based on clock gating with a “quiet” period between the two clocks.
  • Clock toggling detection so the mux can change even if one clock is not toggling.
  •  Select signal change triggers the switch sequence. Assuming slow enough change.
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