Synchronizers

slow signals synchronizer (35 Credits)

Slow signal synchronizer offers a solution for transferring relatively slow and static vectors across clock domains without risking meta-stability and coherency problems resulting from partial vector synchronization. The synchronizer is most suitable for configuration and status synchronization. This component contains a verified RTL code of the bidirectional slow signal synchronizer with parametric data bus width in each direction. The purpose of the slow signal synchronizer is to transfer slow changing signals between two clock domains.
Asynchronous FIFO synchronizer (35 Credits)

Asynchronous FIFO synchronizer offers a solution for transferring signals and vectors across clock domains without risking meta-stability and coherency problems resulting from partial vector synchronization. The synchronizer is suitable for synchronization of data and control information between asynchronous domain of known data and clock ratio. This component contains a verified Verilog RTL code of the asynchronous FIFO synchronizer with parametric data bus width.