Queuing

  • Weighted round robin multi-FIFO queuing (50 Credits)
      A queuing structure is based on a set of FIFOs, storing data from different sources and an arbitration mechanism selecting the most suitable requestor according to a predefined algorithm. This component implements a queuing system based on FIFOs and a weighted round robin arbitration scheme. The typical usage of this queuing structure is to buffer data from multiple sources, select the highest priority and drive it to a shared resource such as a communication link or processing unit. This component contains the verified RTL Verilog code of the FIFO structure and a round robin arbiter.
  • Deficit round robin multi-FIFO queuing (45 Credits)
    This design is a queuing system based on FIFOs and deficit round robin arbitration (DRR). The typical usage of this queuing structure is to store data from multiple sources, select one of them according to the deficit fair arbitration method and drive it to a shared resource such as a communication link or processing unit. This component contains the verified RTL Verilog code of the FIFO structure and the deficit work conserving round robin arbiter.
  • Linked list queuing (50 Credits)
    A linked-list based queuing system manages the enqueue, dequeue and arbitration actions for a multiple queue structure implemented using a single embedded SRAM memory array. This component contains the verified RTL Verilog code of the memory structure and round robin arbiter and implements a queuing system based on dynamically allocated memory per queue. The implementation is based on a linked list concept where each queue is allocated memory locations according to its accumulating size, using the memory space most efficiently.