Clock dividers generate slower clocks from a faster reference clock. The simplest clock divider divides a clock frequency by 2 using a single flop and an inverter. Using the same concept, a counter based clock divider can divide a clock by 2, 4, 8, etc. This component contains RTL Verilog code for clock dividers based on counters. The dividers are used for generating lower frequency clocks from a faster reference clock.