Clocking&Reset

  • Clock dividers generate slower clocks from a faster reference clock. The simplest clock divider divides a clock frequency by 2 using a single flop and an inverter.  Using the same concept, a counter based clock divider can divide a clock by 2, 4, 8, etc. This component contains RTL Verilog code for clock dividers based on counters. The dividers are used for generating lower frequency clocks from a faster reference clock.
  • A clock glitch-free clock multiplexer serves to switch between two asynchronous clocks while protecting downstream logic from clock glitches. The de-glitch clock mux also enables switching when one or both of the clocks are not toggling. This component contains the verified RTL code of the clock switch as well as documentation and timing and physical design instruction. Clock multiplexing is required for clean transition from one clock source to another. The main issue with clock multiplexing is to prevent glitches or unexpected clock pulse that may be too short for parts of the logic.
  • The frequency counter can be used for measuring clock rates, of external or internally generated clocks for the many purposes, such as configuration, validation tasks and more. The measured clock is treated as asynchronous to the control clock and any clock frequency relation can be measured. This component contains RTL Verilog code for a frequency counter designed to measure the frequency of a clock.
  • This component contains verified RTL Verilog code for a process monitor counter designed to measure the frequency of a ring oscillator output for the purpose of correlating process voltage and temperature between devices and measuring on-chip variation (OCV). A ring oscillator is a device composed of an odd number of logical inverters whose output oscillates between the two logical levels. A frequency counter is used for measuring the ring oscillator rates. The measured signal is treated as asynchronous to the control clock and any clock frequency relation can be measured.