FIFOs

  • Basic FIFO (5 Credits)
    FIFO is an acronym for First In, First Out data organization method. FIFOs are widely used in logic design for buffering, queuing and management of rate, priorities and flow control in data applications. A FIFO consists of a read pointer and a write pointer, pointing to entries in a storage array typically, made of flip-flops.
  • Generic FIFO (25 Credits)
      A “generic FIFO” is a reference name to the simple type of synchronous FIFOs, where the memory array is based of flip-flops and the pointers and status (full, empty, almost full etc.) are generated using counters or pointers logic.
  • memory based FIFO (35 Credits)
    A “Memory Based FIFO” is a reference name to the simple type of synchronous FIFOs, where the memory array is based on an embedded memory and the pointers and status (full, empty, almost full etc.) are generated using counters or pointers logic. The memory based FIFO can be used where a large storage is required for a FIFO while keeping the characteristics of a pipeline FIFO. The meaning is that whan the FIFO is empty; there is a one cycle delay from FIFO load to FIFO extract. This enables integration of the FIFO into a pipeline with practically no changes to the pipeline behavior.
  • Gearbox width rate converter FIFO (65 Credits)
    A Gearbox FIFO is a component which allows the conversion of data bus width from input to output. Data of W width, written to FIFO can be read, depending on configuration, as W*N or W/N width vectors where N is natural number providing the rate of read and write match the required data bus width change. The component supports three versions of clocking and rate modes.
  • MUltiple FIFO in one memory array (55 Credits)
    The Multiple FIFO component is a device which allows hosting multiple FIFO queues of the same depth within a single memory structure. Only one FIFO can be written and read in each clock cycle. Each load or extract request is qualified with the number of the FIFO to which it refers. Multiple FIFO control logic can be connected to a two port (1 write/1 read) memory structure with write latency of up to 4 cycles and read latency in range from 1 to 4 cycles. Status flags of FIFOs are designed to keep memory data coherence what is useful especially in case of different write and read latencies.